LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_signed.ALL;

ENTITY testBench IS
END testBench;

ARCHITECTURE testbench_a OF testBench IS
COMPONENT alu32bit IS
	port(a, b 						: IN std_logic_vector(31 downto 0);	-- a and b are busses
		operation 					: IN std_logic_vector(4 downto 0);
		CLK							: IN std_logic;
		z,c 						: OUT std_logic;
	    f 							: OUT std_logic_vector(31 downto 0));
END COMPONENT;

signal TestA, TestB		             : std_logic_vector(31 downto 0);
signal TestOp                     : std_logic_vector(4 downto 0);
signal TestC, TestZ, TestClk      : std_logic;
signal TestF			                   : std_logic_vector(31 downto 0);
begin
process
begin
TestA <= "11111111111111111101110111011101";
TestB <= "11011101110111011111111111111111";
wait for 50 ns;

TestOp <= "00000";
wait for 50 ns;
TestOp <= "00001";
wait for 50 ns;
TestOp <= "00010";
wait for 50 ns;
TestOp <= "00011";
wait for 50 ns;
TestOp <= "00100";
wait for 50 ns;
TestOp <= "00101";
wait for 50 ns;
TestOp <= "00110";
wait for 50 ns;
TestOp <= "00111";
wait for 50 ns;
TestOp <= "01000";
wait for 50 ns;
TestOp <= "01001";
wait for 50 ns;
TestOp <= "01010";
wait for 50 ns;
TestOp <= "01011";
wait for 50 ns;
TestOp <= "01100";
wait for 50 ns;
TestOp <= "01101";
wait for 50 ns;
TestOp <= "01110";
wait for 50 ns;
TestOp <= "01111";
wait for 50 ns;
TestOp <= "10000";
wait for 50 ns;
TestOp <= "10001";
wait for 50 ns;
TestOp <= "10010";
wait for 50 ns;
TestOp <= "10011";
wait for 50 ns;
wait;
end process;

process
begin
testCLK <= '0';
wait for 25 ns;
testCLK <= '1';
wait for 25 ns;
end process;

UUT: alu32bit port map(Clk => TestClk, a => TestA, b => TestB, z => TestZ, c => TestC, operation => TestOp, f => TestF);
end testbench_a;